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Experts in circuit boards
![HDI-Multilayer 8 layers - [1+6+1]](/img/custom/ksg-airview.jpg)
Layer structure
| Pressed board thickness* | 1.48 +/- 10% |
| Overall thickness incl. galv. Cu and solder resist mask* | 1.59 +/- 10% |
Notes on layer structure:
- * Thickness calculation with filled FR-4 base material at 50% copper allocation on the inner layers (depending on base material type, selected copper thickness and copper allocation, deviating resultant insulation and end thicknesses)
- Thickness tolerance of base material +/-10%
- Minimum copper end thicknesses in accordance with IPC 6012, current edition
Design rules for layer structuring
| Through-holes [A] (vias) |
End Ø Via pad Ø |
≥ 200 µm ≥ 500 µm |
| Laser blind holes [B] (blind vias) |
End Ø Via pad Ø |
≥ 100 µm ≥ 350 µm |
| Core holes [C] (buried vias) |
End Ø Via pad Ø |
250 µm ≥ 550 µm |
| Conductive pattern, outer layers |
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| Conductor width with 9 µm copper base Conductor spacing with 9 µm copper base |
≥ 80 µm ≥ 100 µm |
|
| Standard |
Conductor width with 18 µm copper base Conductor spacing with 18 µm copper base |
≥ 100 µm ≥ 120 µm |
| Conductive pattern, galvanised inner layers |
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|
Conductor width with 9 µm copper base |
≥ 100 µm |
|
|
Standard |
Conductor width with 18 µm copper base |
≥ 115 µm |
| Conductive pattern, inner layers | ||
| Conductor width with 18 µm copper base Conductor spacing with 18 µm copper base |
≥ 65 µm ≥ 80 µm |
|
| Standard |
Conductor width with 35 µm copper base Conductor spacing with 35 µm copper base |
≥ 85 µm ≥ 100 µm |